In recent years, with the demand for higher performance and miniaturization of electronic equipment, higher density and higher function for packages in which semiconductor chips are mounted have been desired increasingly. Furthermore, there also is an increasing demand for smaller and higher-density circuit boards on which they are mounted. However, with conventional multilayered circuit boards including glass fiber and an epoxy resin (glass-epoxy multilayered circuit boards) having a penetrating through hole structure formed by drilling, it has become difficult to achieve the high-density packaging. Accordingly, instead of the conventional glass-epoxy multilayered circuit boards, circuit boards that allow a connection not by the penetrating through hole but by an inner via hole have been developed actively (for example, JP 6(1994)-268345 A and JP 7(1995)-147464 A).
However, with the current state of the art, even the high-density mounted circuit boards having such an inner via hole structure cannot keep up with the miniaturization of the semiconductor chips. For example, although the pitch of lead electrodes has become as fine as about 50 μm as the wiring of the semiconductor chips becomes finer, the wiring pitch of the circuit boards and the via hole pitch still are about 100 μm. Therefore, the space for leading out the electrodes from the semiconductor chips increases, thus becoming an obstacle to miniaturization of the semiconductor packages.
Also, since the circuit boards are formed with a resin-based material, they have a low thermal conductivity. Thus, as the component packaging achieves a higher density, it becomes more difficult to dissipate heat that is generated from these components. The dock frequency of CPUs is expected to become about 1 GHz in the year 2000, and with the accompanying higher function thereof, the power consumption of the CPUs is expected to reach 100 to 150 W per a chip.
Furthermore, along with the increase in speed and density, it has become difficult to ignore the influence of noise.
Therefore, in circuit boards, not only the improvement of density and function resulting from a finer circuitry but also anti-noise characteristics and heat dissipation characteristics have to be taken into account.
On the other hand, as a form of responding to the miniaturization of the semiconductor chips described above, a chip size package (CSP) has been suggested. In this CSP, a semiconductor chip is flip-chip mounted on a circuit board called an interposer whose back surface has grid electrodes formed two-dimensionally thereon, and electrodes of the semiconductor chip and the grid electrodes are connected via via holes in the circuit board. This makes it possible to lead out the electrodes of the semiconductor chip that have been formed to have a pitch of not more than 100 μm from the grid electrodes having a pitch of about 0.5 to 1.0 mm, allowing an increase in the pitch of the lead electrodes.
As a result, the need for the finer circuit board on which the CSP is mounted has somewhat reduced, and thus inexpensive circuit boards can be used. Moreover, there is an advantage that the CSP can be used as a tested semiconductor package whose reliability is guaranteed. Consequently, compared with a bare chip technique in which a semiconductor bare chip is mounted on a circuit board directly, the cost required for testing chip damages and defective elements and for ensuring the reliability can be reduced while achieving the miniaturization, which is an advantage of the bare chip mounting.
The development of the CSP described above contributes to an advancement of the miniaturization of the semiconductor package.
On the other hand, in information terminals represented by a mobile personal computer and a mobile phone that can deal with information personally thanks to the development of the internet, the demand for smaller and thinner equipment has been intensified. The typical equipment includes a card-size information terminal, in particular. For example, it is expected to be applied more broadly to card-size radio equipment, a mobile phone, a personal identification card and a memory card for music delivery other than to a current credit card. Thus, a thin semiconductor package or active component that can be mounted on the card-size information terminal mentioned above is desired strongly.
When the above-described CSP is used for achieving a thinner semiconductor package, the bump height in the case of flip-chip mounting, or the wire height and the thickness of a sealing resin in the case of wire bonding, will be added to the thickness of the semiconductor chip (about 0.4 mm) and that of the interposer as the circuit board, resulting in the total thickness of about 0.7 mm. Since the total thickness required for the card-size equipment is about 0.3 to 1.0 mm, the semiconductor package has to be still thinner.
The thickness of the semiconductor package can be reduced by TAB (tape automatic bonding) mounting. An opening and a wiring pattern made of a copper foil are formed on a tape-like film of such as polyimide, a semiconductor chip is mounted in the opening, and electrodes protruding toward the opening directly are bonded to electrodes of the semiconductor chip (inner lead bonding). Similarly, electrodes are led out by connecting electrodes protruding from the tape with the circuit board (outer lead bonding). In this manner, the semiconductor package having a thickness substantially equal to the tape thickness (about 100 μm) can be obtained. In some cases, the form of superimposing multiple layers of this TAB mounted product also is suggested.
In any methods, it is needless to say that the semiconductor chip should be as thin as possible, but since the one (a silicon semiconductor, in particular) with a thickness of not more than 100 μm has a poor mechanical strength, such a semiconductor chip sometimes is damaged during the flip-chip mounting, in which a load is applied. Also, when a semiconductor wafer is abraded to be thinner, its mechanical strength decreases, so that the wafer is more likely to break in a later dicing. On the other hand, after being subjected to dicing, it is extremely difficult and economically inefficient to abrade a small semiconductor chip to be thinner.
On the other hand, the thickness of the semiconductor chip can be reduced by prior dicing. In the prior dicing, the semiconductor wafer is diced halfway of its thickness from one surface, and then is abraded from the other surface until reaching the diced portion. This method can provide a semiconductor chip that is cut automatically after abrading. However, even with this method, because each of the semiconductor chips is thin, a load cannot be applied thereto, leading to a difficulty in dealing at the time of mounting.
Also, in the mobile phone or the like, a surface acoustic wave device is used as a component part of a filter for extracting a specific frequency component.
FIG. 7 is a sectional view showing one example of a structure of a conventional surface acoustic wave device built-in module including two surface acoustic wave devices having a filter function. This module is used as, for example, an antenna duplexer used in a radio portion of a mobile phone or the like.
In FIG. 7, numeral 601 denotes surface acoustic wave devices, numeral 602 denotes piezoelectric substrates, numeral 603 denotes comb-shaped electrodes, numeral 604 denotes lead-out electrodes, and numeral 605 denotes metal bumps. Numeral 607 denotes a circuit board, numeral 609 denotes first wiring patterns, numeral 610 denotes second wiring patterns, numeral 611 denotes via holes, numeral 612 denotes a cover, numeral 613 denotes a sealant, numeral 614 denotes internal circuits, and numeral 615 denotes a concave portion.
In the surface acoustic wave device 601, on one surface of the piezoelectric substrate 602 formed of, for example, lithium tantalate, lithium niobate or quartz, the comb-shaped electrode 603 and the lead-out electrodes 604 formed of a metal film containing aluminum as a main component are formed. The metal bumps 605 for an electrical connection with an external circuit are formed on the lead-out electrodes 604.
The circuit board 607 has the first wiring patterns 609 on one surface, the second wiring patterns 610 on the other surface and the internal circuits 614 therein. The first wiring pattern 609, the second wiring pattern 610 and the internal circuit 614 are connected by the via holes 611. A plurality of the surface acoustic wave devices 601 built into the module shown in FIG. 7 and the external circuit are connected via these elements. In order to ensure a space in which the surface acoustic wave devices 601 are mounted, the circuit board 607 has the concave portion 615 in its central portion.
After the surface acoustic wave devices 601 are positioned and placed on the circuit board 607, the first wiring patterns 609 and the metal bumps 605 are electrically connected. When gold bumps are used as the metal bumps 605, heat and ultrasonic wave are used in combination so as to melt the metal bumps 605 for the connection. Alternatively, there also is a case of making the connection using an electrically conductive adhesive. Also, when solder bumps are used as the metal bumps 605, the connection is made by reflowing the solder bumps.
Since the surface acoustic wave device 601 is sensitive to an influence of an external atmosphere, the concave portion 615 of the circuit board 607 finally is sealed airtightly with, for example, the cover 612 formed of a metal plate and the sealant 613 formed of a solder or an adhesive. In this manner, the surface acoustic wave device built-in module used for an antenna duplexer or the like is obtained.
In the above description, as the piezoelectric substrate 602 constituting the surface acoustic wave device 601, a wafer having a thickness of 0.3 to 0.4 mm is used normally. Thus, the conventional surface acoustic wave device built-in module has a thickness of about 1 mm, making it difficult to reduce the thickness of electronic equipment represented by a mobile phone.
Accompanying a rapid advancement of mobile communication equipment in recent years, a still thinner module has been required, leading to an increase in demand for reducing the thickness of the piezoelectric substrate 602. However, since a single crystal material such as lithium tantalate, which is used as the piezoelectric substrate 602, is brittle and easy to break, it is very difficult to use the piezoelectric substrate 602 as thin as, for example, about 0.2 mm in practice during wafer transportation in a photolithography process for forming the comb-shaped electrode on the piezoelectric substrate 602 and when dealing with each of the devices in a process of mounting it on the circuit board 607. Furthermore, in the surface acoustic wave device 601, a commonly used technique is that the surface (the surface on a nonfunctional portion side) opposite to that on which the comb-shaped electrode 603 is formed (the surface on a functional portion side) is roughened so as to prevent a deterioration in characteristics caused by a reflection of an elastic wave from the surface on the nonfunctional portion side. When attempting to reduce the thickness of the piezoelectric substrate 602, the wafer is more likely to break also in this process of roughening the surface on the nonfunctional portion side. Accordingly, with the conventional structure, a thinner component built-in module using the surface acoustic wave device has been difficult to achieve.